1. Field
Exemplary embodiments of the present invention relate to a variable resistance memory device and a method for fabricating the same, and more particularly, to a variable resistance memory device with a three-dimensional structure including a plurality of memory cells vertically stacked from a substrate, and a method for fabricating the same.
2. Description of the Related Art
A variable resistance memory device refers to a device which stores data based on such a characteristic that switching function is implemented between different resistance states, each changed according to an external stimulus. The variable resistance memory device includes a resistive random access memory (ReRAM), a phase change RAM (PCRAM) and a spin transfer torque-RAM (STT-RAM). The variable resistance memory device has been researched since it can be formed to a simple structure. Also, the variable resistance memory device may have various excellent properties such as nonvolatility and so forth.
Among variable resistance memory devices, the ReRAM includes a variable resistance layer which is formed of a variable resistance substance, e.g., a perovskite-based substance or a transition metal oxide, and electrodes formed over and under the variable resistance layer. According to a voltage applied to an electrode, filament current paths are created or vanished in the variable resistance layer. When the variable resistance layer becomes a low resistance state, the filament current paths are created. Otherwise, if the variable resistance layer becomes a high resistance state, the filament current paths are vanished. Switching from the high resistance state to the low resistance state is referred to as a set operation. Conversely, switching from the low resistance state to the high resistance state is referred to as a reset operation.
Meanwhile, in order to improve the degree of integration of such a variable resistance memory device, the so-called cross point cell array structure has been suggested. The cross point cell array structure includes plural memory cells located at crossing points between a plurality of bit lines extending in one direction and a plurality of word lines extending in another direction crossing with the bit lines.
However, in order to form the cross point cell array structure, there are concerns in that fabrication processes may be complicated and the fabrication costs increase, because a plurality of mask processes should be repeated to pattern the bit lines and the word lines to a minimum critical dimension.